D>PROGRAM COUNTERPROGRAM COUNTERFUNCTIONAL DESCRIPTIONThe program counter, PC, is aspecial-purpose it is registered that is offered by the processor to holdthe resolve of the next instruction to be executed. The PLA automaticallyupdates the pc to allude to the following instruction during the op-codedecode cycle. By coordinating with other hardware, in additionto the PLA, the computer is immediately incremented as each instructionis executed. The pc can likewise have an resolve dictated to it viathe "BRANCH" instruction. Discovered in number 1 listed below is thefunctional level block diagram of the pc designed for this microprocessor.The pc possesses the adhering to attributes: outputs one 8-bit address,resets come zero, deserve to be invited with any kind of 1 that the feasible 256 addressesand produce an overflow flag if the counter exceeds 256. Whenthe machine is reset, via an external pin, the "/RESET come ZERO"pin is pulled low by the PLA causing the computer being collection to00h. The pc is incremented by the PLA by pulling the "/INCREMENT"pin short for 1 clock cycle. If the pc is incremented past its 256word deal with reach the "OVER flow FLAG" pin will be moved high.The PC can be compelled to a specified value v the use of the"BRANCH" command. Once the PLA decodes a "BRANCH", the pc willlatch in the materials of the next 2 addresses. The processor thenshifts the concatenated 8-bit attend to into the PC.Figure 1REGISTER carry LEVELDESCRIPTIONAs displayed in figure 2, the pc hasseveral materials that help in the task of providing the addressof the next instruction. During a reset, the PLA resets the incrementerto 00h and also then latches the calculation of the incrementer right into thePC. The value included in the pc is then driven out through themultiplexer by the PLA picking the computer data path. Because that each timethe PLA implements one increment PC, the incrementer is advancedby 1 and also then shifted into the computer register. The worth containedwithin the computer is climate selected to pass through the multiplexerwhose output is straight tied to the attend to pins. As soon as the PLAdecodes a "BRANCH" op code, the contents of the following 2 addressesare shifted into the B register via the data bus controller. Oncethe branch address is shifted into the B register the value isthen loaded right into the incrementer. The PLA then proceeds come passthe contents of the B register with the multiplexer to theaddress pins. Top top the next increment PC, the value that to be shiftedinto the incrementer native the B register is incremented, shiftedinto the PC and passed v the multiplexer.Figure 2GATE LEVEL DESCRIPTIONIncrementerThe 8-bit incrementer is baseon the circuit presented in number 3. The incrementer circuithas the ability to it is in reset to 0 and to it is in incremented through 1. The8-bit incrementer is constructed by routing the lug signal aroundto the entry of the and gate the the next incrementer circuit.The LSB of the incrementer has the intake of the and gate tiedto Vdd. The "COUNT" signal that the MSB is offered as the "OVER FLOWFLAG", signifying the the increment has actually exceeded the 8-bit limit.Figure 3S-R LatchThe incrementer circuit supplies anS-R latch to carry out the ability to reset the incrementer come 00hand to latch the existing address. The door level schematic ofthe S-R latch offered in the incrementer architecture is shown listed below infigure 4. The "CLK" and "-CLK" signals are tied to "/INCREMENTPC" and also "INCREMENT PC" respectively. In addition, the "-RESET"is mapped come "/SET to ZERO" in the 8-bit increment design. Inthe silicon implementation the the 8-bit incrementer, the "CLK"and "-CLK" signal were heavily buffered to ensure that risingand falling edge of this signal included very little skew.In addition, the "-SET" signal to be tied come Vdd due to the fact that it had noapplication in this design. Number 4MultiplexerThe multiplexer offered in the PCdesign is used to pass either the computer register or the B register.The 16-to-8 multiplexer was built by concatenating 8 2-to-1multiplexer. As shown in figure 5 the 2-to-1 multiplexer is bufferedby implementing 2 inverters at the output of the multiplexer.The final style of the 16-to-8 multiplexer is designed such thatonly 1 manage signal is offered by the PLA come either happen thePC register or the B register.Figure 5Bidirectional Bus ControllerThe bidirection bus controlleris offered to enable the 4-bit addresses to it is in latched native the databus right into the B register. When the PLA is executing a "BRANCH"instruction the attend to of the place to be branch come is latchinto the B register. Once the PLA is no latching a value intothe B register the bidirection bus controller is put into hi-zstate. The hi-z state is essential to ensure that the data busis not greatly loaded as soon as the B register is not latching datain.Figure 6SILICON LEVEL DESCRIPTIONThe silicon level implementationof the PC and associated hardware was completed v minimizationof area as the major focus. Of an additional importance to be speedand the capacity to easily combine with other blocks the the CPU.Great treatment was taken in the layout the the incrementer, multiplexer,and bus controller come ensure that area consumption was in ~ a minimum.Examples of an excellent layout techniques that were enforced in thedesign of the computer are as follows: overlay that power and ground supplies,weaving the buses, usage of poly for regional connections and all portsbrought the end to periphery of components. Every individual componentwas completely tested native the transistor level up to the functionallevel. The was uncovered through testing that the performance of the8-bit incrementer might be amplified by giving a heavily buffered"/INCREMENT PC" signal from the PLA.
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In the final analysis ofthe PC and associated hardware that was found to be totally functionaland performed come specifications.PC time CIRCUITRY presented in number 7 below is therequired time circuitry supplied to coordinate between the incrementerand the pc register. The timing circuitry ensures the the PCwill latch the value driven by the incrementer one-half cycleafter the incrementer has been reset come zero or incremented.Figure 7Back to the front pageOn to following page...